This patent document relates to techniques, devices, and systems for digital phase locked loops in digital circuits and electronics, digital signal processing and communications.
A digital phase locked loop (DPLL) can be formed by a digitally controlled oscillator (DCO) that generates a high frequency clock signal based on a digital input control word. A digital feedback loop can use the DCO-produced high frequency clock signal to generate a feedback signal and a time-to-digital converter (TDC) as a digital phase detector to determine a phase difference between the DCO-produced high frequency clock signal and a low frequency reference clock signal. This phase difference is sent into subsequent digital processing stage of the DPLL which includes a digital loop filter that generates the digital input control word to the DCO for generating the high frequency clock signal.